module Mux14to7_1bit(ip7,self7,op7,enable);

input [6:0]ip7, self7;
input enable;
output [6:0]op7;

Mux2to1_1bit mux00(ip7[0],self7[0],op7[0],enable);
Mux2to1_1bit mux01(ip7[1],self7[1],op7[1],enable);
Mux2to1_1bit mux02(ip7[2],self7[2],op7[2],enable);
Mux2to1_1bit mux03(ip7[3],self7[3],op7[3],enable);
Mux2to1_1bit mux04(ip7[4],self7[4],op7[4],enable);
Mux2to1_1bit mux05(ip7[5],self7[5],op7[5],enable);
Mux2to1_1bit mux06(ip7[6],self7[6],op7[6],enable);

endmodule
